1. Field of the Invention
This invention relates to a logic circuit and particularly to a logic circuit having a Manchester-type carry chain.
2. Description of the Prior Art
FIG. 2 shows a conventional multistage adder having a Manchester-type carry chain. In the figure, each full adder 1 comprises input terminals 2 and 3, an addition result output terminal 4, a carry input terminal 5, and a carry output terminal 6.
In each of the full adders 1 constituting the multistage adder, when input signals enter the input terminals 2 and 3 and the carry input terminal 5, the results of the following operations appear at the addition result output terminal 4 and carry output terminal 6. EQU Si=Ai.sym.Bi.sym.Cin (1) EQU Cout=Ai.multidot.Bi.sym.Ai.multidot.Cin.sym.Bi.multidot.Cin (2)
where .crclbar. is a symbol for exclusive-OR operation. Herein, Ai, Bi (i=0, 1, . . . n) are input signals to said full adders, Cin is a carry input signal, Cout is a carry output signal, and Si (i=0, 1, . . . n) is an addition result output signal.
Now, a case will be considered in which the following addition is performed. EQU S=A.sym.B.sym.C.sub.0
where S=S.sub.0 .about.S.sub.n, A=A.sub.0 .about.A.sub.n, and B=B.sub.0 .about.B.sub.n.
First, bit values Ai and Bi for input signals A and B are inputted to each full adder 1. An initial carry input signal C.sub.0 is inputted from the carry input terminal 5 to the first stage full adder 1.
In the first stage full adder 1, the operations indicated by the equations (1) and (2) are performed and the addition result output signal S.sub.0 and carry output signal Cout are outputted from the addition result output terminal 4 and carry output terminal 6, respectively. In the second stage full adder 1, logic operations are performed using input bit values A.sub.1 and B.sub.1 together with the carry output signal Cout from the first stage, and the addition result S.sub.1 is outputted while the carry output signal Cout is fed to the subsequent stage. Similarly, the carry from the preceding stage is transferred to the subsequent stage for logic operation until the last stage is reached whereupon the operation is completed and the last stage carry output signal C.sub.n is outputted.
In addition, such a Manchester-type carry chain as is described above is disclosed on pp 22, 23, 150 and 151 of "INTRODUCTION TO VLSI SYSTEM," by Carver Mead and Lynn Conway.
Since the conventional full adder having the Manchester-type chain are constructed in the manner described above, logic operations on bits cannot be started in each stage until a carry is transferred from the preceding stage.
Therefore, the computing speed is limited by the carry transmission time; it becomes lower as the number of bits increases.